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Dual Synchronous Buck Pseudo Fixed Frequency DDR Power Supply Controller
POWER MANAGEMENT Description
The SC1486 is a dual output constant on synchronousbuck PWM controller optimized for cost effective mobile DDR applications. Features include high efficiency, a fast dynamic response with no minimum on time, a REFIN input and a buffered REFOUT pin capable of sourcing 3mA. The excellent transient response means that SC1486 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. The output voltage of the first controller can be adjusted from 0.5V to VCCA. In DDR applications, this voltage is set to 2.5 volts. A resistor divider from the 2.5 volt supply is used to drive the REFIN pin of the second controller. A unity gain buffer drives the REFOUT pin to the same potential as REFIN. The second controller regulates its output to REFOUT. Two frequency setting resistors set the on-time for each buck controller. The frequency can thus be tailored to minimize crosstalk. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-bycycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output for each controller.
SC1486
Features
Constant on-time for fast dynamic response VIN range = 1.8V - 25V DC current sense using low-side RDS(ON) sensing or sense resistor Integrated reference buffer for VTT Low power S3 state Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start PSAVE option for VDDQ Over-voltage/under-voltage fault protection <20uA shutdown current Low quiescent power dissipation Two separate PGOOD indicators Separate enable of each switcher Integrated gate drivers with soft switching Efficiency >90% 1% Internal reference 28 Lead TSSOP Industrial temperature range
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
R1 VBAT 23 R2 9 VDDQ/2 8 10 22 TON2 REFIN TON1
PGOOD1
27 13
PGOOD2 VBAT PGOOD1
SC1486
PGOOD2
Q4 REFOUT REFOUT EN/PSV1 DH2 LX2 ILIM2 Q1 6 5 R3 4 R4 R11 1 PGND1 R10 R5 PGND1 + C7 Q2 2 ILIM1 DL1 FBK2 FBK1 12 26 PGND1 DH1 LX1 DL2 PGND2 20 19 R8 18 16 15 Q3 + C8
EN1
L2 VTT, 1.25V
VDDQ, 2.5V
L1
Revision 5, January 2003
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SC1486
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter TON1 to AGND1, TON2 to AGND2 DH1, BST1 to AGND1 and DH2, BST2 to AGND2 LX1 to AGND1 and LX2 to AGND2 AGND1 to PGND1, and AGND2 to PGND2 BST1 to LX1 and BST2 to LX2 VCCA1, VDDP1 to AGND1 and VCCA2, VDDP2 to AGND2 FB1, PGOOD1, EN/PSV1, ILIM1, VOUT1, DL1 to PGND1 FB2, PGOOD2, REFIN, ILIM2, REFOUT, DL2 to PGND2 Thermal Resistance Junction to Ambient(5) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V V C/W C C C
JA TJ TSTG TLEAD
37 -40 to +125 -65 to +150 300
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies V C C A 1, V C C A 2 V D D P 1, V D D P 2 VDDP2 Undervoltage Threshold VDDP2 Undervoltage Hysteresis VDDP1 Operating Current VDDP2 Operating Current VCCA1, VCCA2 Operating Current VCCA2 Standby Current TON1, TON2 Operating Current REFIN Bias Current Shutdown Current FB > regulation point, ILOAD = 0A VDDP2 < VDDP2 UV threshold, no load on REFOUT RTON = 1M REFIN = 1.25 EN/PSV1 = 0V V C C A 1, V C C A 2 TON1, TON2, VDDP1
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5.0 5.0 VDDP2 falling 3.5 250 FB > regulation point, ILOAD = 0A 1 5 700 125 15
4.5 4.5
5.5 5.5
V V V mV
5 10 1100
A
A A A
1 -5 5 0 -10 10 1
A A A A
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SC1486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Controller Error Comparator Threshold (FBK1 Turn ON Threshold) VDDQ Output Voltage Range REFOUT Source Capability REFOUT DC Accuracy Error Comparator Threshold (FBK2 Turn ON Threshold) On-Time, VBAT = 2.5V no load, REFIN = 1.25 VCCA = 4.5V to 5.5V VBAT = 2V to 25V RTON = 1M (300kHz), VOUT = 1.25V RTON = 500K (600kHz), VOUT = 1.25V Minimum Off Time VOUT Input Resistance (VDDQ Controller) Line Regulation Error Load Regulation Error FBK1 Input Bias Current FBK2 Input Bias Current Over-Current Sensing ILIM Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection Current Limit (Positive) (PGND-LX)
(2)
VCCA = 4.5V to 5.5V VBAT = 2V to 25V
0.500
0.495 0.5 3
0.505 VC C A
V V mA
1.24
REFOUT
1.26
1.238
REFOUT -10mV
1.262
REFOUT +10mV
V V ns ns ns k %/V %
1660 913 400 500
1411 776
1909 1050 550
VCCA, VDDP = 4.5V to 5.5V VBAT = 4.5V to 25V ILIM - PGND = 0V to OC Limit EN/PSV1 = Open
0.04 0.3 -1.0 2.5 +1.0
A A
10 PGND - ILIM
9 -10
11 +10
A mV
PGND - LX EN/PSV1 = 5V
5
mV
RILIM = 5k RILIM = 10k RILIM = 20k
50 100 200 -140
-35 80 170 -200
65 120 230 -100
mV mV mV mV
Current Limit (Negative) (PGND-LX)
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SC1486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Fault Protection (Cont.) VDDQ - Output Under-Voltage Fault VTT - Output Under-Voltage Fault VDDQ/VTT Output Over-Voltage Fault With respect to internal reference With respect to REFOUT VDDQ with respect to internal reference, VTT with respect to REFOUT FB forced above OV threshold Sink 1mA FB in regulation, PGOOD = 5V With respect to internal reference for VDDQ and REFOUT for VTT FB forced outside PGOOD window. Falling (100mV hysteresis) 10C Hysteresis -10 -15 -30 -20 +10 -40 -28 +8 -25 -15 +12 % % %
Over-Voltage Fault Delay PGOOD Low Output Voltage PGOOD Leakage Current PGOOD UV Threshold
2 0.4 1 -8
s V A %
PGOOD Fault Delay VCCA1,VCCA2 Under Voltage Over Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage REFIN EN Threshold REFIN EN Hysteresis EN/PSV1 Input Resistance
2 4.0 165 3.7 4.3
s V C
EN/PSV1 low EN High, PSV low (Pin Floating) EN/PSV1 high 0.80 40 Pullup resistance Pulldown resistance 1.5 1.0 2.0 1.2 2.4 0.55
1.2 2.4
V V V
1.00
V mV M
Soft Start Soft-Start Ramp Time Under-Voltage Blank Time EN/PSV1 high to full current limit. SMPS turn-on 1.6 2 ms ms
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SC1486
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Gate Drivers Shoot-Through Delay (4) DL Pull-Down Resistance DL Pull-Up Resistance DH Pull-Down Resistance DH Pull-Up Resistance DH or DL rising DL low DL high DH low, BST - LX = 5V DH high, BST - LX = 5V 30 0.8 2 2 2 1.6 4 4 4 ns
Notes: (1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below. (5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
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SC1486
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
DEVICE SC1486ITSTR SC1486ITSTRT(2) PACKAGE(1) TSSOP-28 TSSOP-28
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free option.
(TSSOP-28)
Pin Descriptions
Pin # 1 2 3 4 Pin Name PGND1 D L1 VD D P1 ILIM1 Pin Function Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Reference input. A resistor divider from the 2.5 volt supply sets this voltage. A 0.1 F input filter capacitor is reccomended. Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. Buffered REFIN output. The second controller regulates to this voltage. Supply voltage input for the analog supply. Connect through a RC filter. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground.
5 6 7 8 9 10 11 12 13 14
LX 1 DH1 BST1 REFIN TON2 REFOUT VC C A2 FB K 2 PGOOD2 AGND2
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SC1486
POWER MANAGEMENT Pin Descriptions (Cont)
15 16 17 18 PGND2 D L2 VD D P2 ILIM2 Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Enable/Power Save input pin. Tie to ground to disable SMPS. Tie to +5V to enable SMPS and activate PSAVE mode. Float to Enable SMPS and activate continous conduction mode. Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. Output voltage sense input for the SMPS output. Connect to the output of the SMPS. Supply voltage input for the analog supply. Connect through a RC filter. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground.
19 20 21 22 23 24 25 26 27 28
LX 2 DH2 BST2 EN/PSV1 TON1 VOUT1 VC C A1 FB K 1 PGOOD1 AGND1
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SC1486
POWER MANAGEMENT Block Diagram
PGND1 1 DL1 2 VDDP1 3 LO
REF - 30% REF - 10% REF + 10% UV OV FAULT MONITOR
AGND1 28
PGOOD1
27
+5V
ILIM1 4 ISENSE
ZEROI OC
FB1 CONTROL LOGIC PWM OFF ON HI
REF
LX1 5 VDDQ DH1 6 BST1 7
OT VBAT VDDQ = 2.5V VCCA2 VDDQ VDDP2 VDDP
8 REFIN
POR/SS
OT 21 BST2 HI 20 DH2 19 LX2
VREF
9 TON2 10 REFOUT 11 VCCA2
TON
ON OFF PWM REF BUFFER
CONTROL LOGIC
+5V
TOFF
OC ZEROI 12 FBK2 VTT 17 VDDP2 13 PGOOD2 14 AGND2 FAULT MONITOR OV UV REF + 10% REF - 10% REF - 30% LO 16 DL2 15 PGND2 + + PWM +5V ISENSE 18 ILIM2
FIGURE 1 - SC1486 Block Diagram
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+ 1.5V TOFF TON POR/SS VCCA1
PWM
FBK1 X3 26 FB1
VCCA1 25 VOUT 24 TON1 23 VDDQ +5V
EN/PSV1 22
VBAT VCCA VDDP VDDQ
VTT
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SC1486
POWER MANAGEMENT Application Information
+5V Bias Supplies The SC1486 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951A. To minimize channel to channel crosstalk, each controller has 4 supply pins, VDDP, PGND, VCCA and AGND. To avoid ground loops, separate AGND planes are recommended. Each contoller requires its own AGND plane which should be tied by a single trace to the negative terminal of that controller's output capacitor. All external components referenced to AGND in the schematic should then be connected to the appropriate AGND plane. The supply decoupling capacitor for controller 1 should be tied between VCCA1 and AGND1. Likewise, the supply decoupling capacitor for controller 2 should be tied between VCCA2 and AGND2. A single 10 ohms resistor should be used to decouple the VCCA supplies from the main VDDP supplies. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to this plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, the two AGND planes must be connected to the PGND plane at the negative terminal of the respective output capacitors. The VDDP1 and VDDP2 input provides power to the upper and lower gate drivers. A decoupling capacitor for each supply is recommended. No series resistor between VDDP and the 5 volt bias is required. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The TON time is the time
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required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator.
V TON = 3.3x10-12 * (RTON+ 37x103 ) * OUT +50ns V IN
RTON is a resistor connected from the input supply to the TON pin. Enable & Psave The EN/PSV pin enables the VDDQ (2.5 volt) supply. REFIN and VDDP2 enable the VTT (1.25 volt) supply. The VTT and VDDQ supplies may be enabled independently. When EN/PSV is tied to VCCA the VDDQ controller is enabled and power save will also be enabled. When the EN/PSV pin is tristated, an internal pulled-up will activate the VDDQ controller and power save will be disabled. If PSAVE is enabled, the SC1486 PSAVE comparator will look for the inductor current to cross zero on eight consecutive cycles. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve the efficiency and add hysteresis, the on time is increased by 50% in power save. The efficiency improvement at light loads more than offsets the disadvantage of slighlty higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled.Since the VTT supply must sink current, this controller does not have a power save option. If REFIN is low, the VTT controller shuts down to a low bias current. If Refin is greater than 1 volt, and VDDP2 is low, the reference buffer is active, but the VTT buck converter is disabled (S3 state). If REFIN is greater than 1 volt and VDDP is greater than 4 volts, the VTT supply is active. Output Voltage Selection The output voltage selection is set by the feedback resistors R2 & R3 of Figure 3. The internal reference is 1.5V. The internal feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can beselected to a minimum of 0.5V. The equation for setting he output voltage based on Figure 3 is:
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SC1486
POWER MANAGEMENT Application Information (Cont.)
R2 Vout= 1+ *0.5 R3
Current Limit Circuit Current limiting of the SC1486 can be accomplished in two ways. The on-state resistance of the low-side MOSFETs can be used as the current sensing element or sense resistors in the low-side sources can be used if greater accuracy is desired. RDSON sensing is more efficient and less expensive. In both cases, the RILIM resistors between the ILIM pin and LX set the over current threshold. This resistor RILIM is connected to a 10uA current source within the SC1486 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIMresistor, current limit will activate. The high side will not be allowed to turn on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. The current sensing circuit actually regulates the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
BST DH LX ILIM VDDP DL PGND
+5V
+VIN
D1
+
C1
Q1 C2 L1 Vout
R1 Q2
D2
+
C3
FIGURE 3
The schematic of RDSON sensing circuit is shown in Figure 3 with RILIM = R1 and RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM.When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current exists and the high side MOSFET will not be allowed to turn on. The over-current equation when using an external sense resistor is:
IL OC (Valley ) = 10 A * R ILIM R SENSE
Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R4.
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
BST DH LX ILIM VDDP DL PGND
+5V
+VIN
D1
+
C1
C2
Q1 L1 Vout
D2 Q2
+
C3
TIME Valley Current-Limit Threshold Point
R1 R4
FIGURE 2
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FIGURE 4
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SC1486
POWER MANAGEMENT Application Information (Cont.)
Power Good Output Each controller has its own PGOOD. Power good is an open-drain output and requires a pull-up resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during start-up and will not be allowed to transition high until soft start is over and the output reaches 90% of its set voltage. There is a 2us delay built into the PGOOD circuit to prevent false transitions. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input, REFIN or VCCA is toggled. There is a 2us delay built into the OV protection circuit to prevent false transitions. A OV fault in either controller will not cause the other one to shutdown. Note: to reset VDDQ from a fault, VCCA1 or EN/PSV must be togled. To reset VTT from a fault, VCCA2 or REFIN must be togled. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input is toggled. There is a 2us delay built into the UV protection circuit to prevent false transitions. An UV fault in either controller will not effect the other controller. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA1 and VCCA2 exceed 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.2V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.1V the output drivers are shutdown and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs.
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An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process.
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SC1486
POWER MANAGEMENT Application Information (Cont.)
Stability Considerations Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a 10pF capacitor across the upper feedback resistor divider network. This is shown below in Figure 5, by capacitor C4 in the schematic. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed.
+5V +VIN
SC1486 ESR Requirements The constant on-time control used in the SC1486 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Refering to Figure 5, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is;
Fs - 200000 1+3 * R2 + R3 Fs * ESR > 2 * * Cout * Fs * ( 1 - D ) 2 R3
D1
+
C1
Q1 C2 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 L1 0.5V - 5.5V
R1 D2 Q2 + C3
R2
C4 10pF
R3 FBK
FIGURE 5
Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is sign that the ESR should be increased.
Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 500nS (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200KHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY = TON(MIN) TON(MIN) + TOFF (MAX )
Be sure to include inductor resistance and MOSFET on-state voltage drops when performing worst-case dropout duty-factor calculations. Layout Guidelines (TBD)
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SC1486
POWER MANAGEMENT Application Information (Cont.)
SC1486 System DC Accuracy (VTT Controller) Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The 1486 regulates to the REFOUT voltage not the REFIN voltage. Since DDR specifications are written with respect to REFOUT, the offset of the reference buffer does not create a regulation error. The error comparator offset is trimmed so that it trips when VOUT is 1.25 volts at room temperature. This offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. The on pulse in the SC1486 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25 volts, then the valley of the output ripple will be 1.25 volts. If the ripple is 20mv with VIN=6, then the DC output voltage will be 1.26 volts. If the ripple is 40mv with VIN=25 volts, then the DC output voltage will be 1.27 volts. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Passive droops also improves stability so it should be used when possible. 1486 System DC Accuracy (VVDQ Controller) Three IC parameters affect system DC accuracy, the internal band gap reference, the error comparator offset voltage, and the switching frequency variation with line and load. The internal 1% 1.5V reference contains two error components, a 0.5% DC error and a 0.5% supply and temperature error. The error comparator offset is trimmed so that it trips when the feedback pin is nominally
2002 Semtech Corp. 13
0.5 volts +/-1% at room temperature. The comparator offset trim compensates for any DC error in the reference. Thus, the percentage error is the sum of the reference variation over supply and temperature and the offset in the error comparator or 1.5%. The on pulse in the SC1486 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mv with VIN = 6 volts, then the measured DC output will be 2.525 volts. If the ripple increases to 80mv with VIN = 25 volts, then the measured DC output will be 2.540. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage.It will not change the frequency. Switching frequency variation with load can be minimized by choosing lower RDSON MOSFETs. High RDSON MOSFETS will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. This inherent droop should be considered when deciding if passive droop is required. If the output ripple some passive droop may be desirable to further reduce the output capacitance.
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SC1486
POWER MANAGEMENT Application Information (Cont.)
DDR Supply Selection The SC1486 can be configured so that VTT and VDQ are generated directly from the battery. Alternatively, the VTT supply can be generated from the VDDQ supply. Since the battery configuration generally yields better efficiency and performance, the eval board is configured to generate both supplies from the battery. DDR Reference Buffer The reference buffer is capable of driving 3ma and sinking 25ua. Since the output is class A, if additional sinking i s required an external pulldown resistor can be added. Make sure that the ground side of this pulldown is tied to the VTT AGND plane near the AGND2 pin of the SC1486. As with most opamps, a small resistor is required when driving a capacitive load. To ensure stability use either a 10 ohm resistor in series with a 1uf capacitor or a 100 ohm resistor in series with a 0.1uF capacitor from REFOUT to AGND2. REFIN should also be filtered so that VDDQ ripple does not appear at the REFIN pin. If a resistor divider is used to create REFIN from VDDQ, then a 0.1uF capacitor from REFIN to AGND2 will provide adequate filtering. Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = 2 * VCCA * IVCCA + Vg * Q g * f
(
)
W
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85C JA = 37C/W VCCA = 5V IVCCA = 1100A (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz (enter the higher of the two set frequencies here) gives us:
TJ = 85 + 2 * 5 * 1100 * 10 -6 + 5 * 60 * 10-9 * 300 * 103 * 37 = 92 C
(
)
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
2002 Semtech Corp.
14
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V _T T POD GO1 VIN _V T T
+5 V_ UN R
C4 1 1 1 22 0u F V _T T 1 10 uF 2 / 5V C 9 2 0.1 uF 2 / 5V Q 2 1 L2 X 3 S i48 18 DY 8 1 TP 0 1 1 33 . uH L 2 2 POD GO1 C0 1 2 TP 1 1 1 + TP 3 2
2
1
5
6
7
2 R 2 1 4 70 k VA BT D2 H +5 V_ UN R 1 R 6 2 C1 1 1 1 0k D2 H L2 X IL M I1 2 D2 L 0.1 uF 2 / 5V B T2 S 0 .1u F R 9 2 1 2 10 00 k C5 1 2 C 6 2 R 3 20 k 1 V CA C FB 1 K M BR 53 0 0 TO 1 1 N 2 1 D 2 N_ O PO P 80 k 1 E N_ SV P D2 L R 4 2 FB 1 K 2 T1 P 1 V 2_ 5 1 1 2 TBR 53 P M 70 0 T9 P
1
C 4 2 0 .1u F
1 9 L2 X
2 6 FB 1 K
2 1 B T2 S
2 0 D2 H
2 5 VC A C1
2 4 VU O T1
2 3 TO 1 N
1 8 IL M I 2
1 7 VD P D2
1 6 D2 L
2 8 A N1 GD
R 1
P N1 GD
D1 L
VD P D1
IL M I 1
L1 X
D1 H
B T1 S
TO 2 N
RE O F UT
VC A C2
FB 2 K
POD GO2
1 1 2 3 1 0 1 1 B T1 S7 D1 L IL M4 I 1 L 15 X D 16 H TO 9 N 2 0 .1u F
1 3
R F_ N E I 8 RE I N F
D 1 2
1 2 2 R 5 2 10 k D1 H 1 D1 L 1 1 0 .1u F 0 .1u F T2 P 1 T4 P D1 L 4 D1 H 3 2 1
D
2 R 7 C 8 7 50 k 2 C2 1 1
C 5 1
V T T1 _ 2
R F_ E RC
2
M BR 53 0 0 C9 1 1
R1 1 1 0.1u F/X 7R 10 0 2
0 .1u F
C 2 VIN _V T T
2
1
10 uF 2 / 5V 4 1
C 1
2
1
1 4
2
A N2 GD
D
1
2
1
+
15
C 3 8 7 6 5 8 7 6 5 3 2 1
1 0
SC1486
2
1
2 7 POD GO1
2 2 E /P V N S1
1 5 P N2 GD
1
4
2002 Semtech Corp.
POWER MANAGEMENT Application Schematic
D 4
R2 1 1 2 N_ O PO P
0.1 uF 2 / 5V
Q 5
IR F7 81 1 T6 P 1 L1 X L1 X
Q 6
D 3 F DS 76 7 4 2
1 TP 2 1 M BR 53 0 0 TP 3 1
L 1 2 uH C 7 2 15 0u F C3 1 T8 P 1 R0 1 1 1 10 k 2
1 R F_ U E OT
1 POD GO2
R3 1 100 0p F/X 7R 2 10 k +5 V_ US S 1 4 70 k 2
+5 V_ SU S
1
T5 P
1 R 8 R F_ N2 E I
VA BT
V 2_ 5 POD GO2 V 25 R F IN E RFOT E U
SC1486
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SC1486
POWER MANAGEMENT Application Schematic
+5 _ U VS S
1 80 G R EEN 3 P G LE D 4 10nF Q3 2N 7 0 02
1
T P 14
Ju pe S m r ett g in s:
I N -- L Ds E a E n ble d ( or al M Nm od ) e O T -- LE s O U D FF ( ia m Bs ea su m n ) re e ts
B E R G _2 P I N J P4
V dd P q W R GO OD
+5V_SU S 1 R 14 2 D5
J1
B _ J A C K _P AIR
1 PO S NE G 2
1 VBA T
T P 15
P G LE D 1 P G LE D 3 2
P G LE D 2 1
2
J2 1 PO S N EG
B _J A C K _ P A I R
VBA T
1 P G LE D 0 1 1 R 15 1 80 2 G R EEN R 16 1 0k
2 1 T P 16
VP tt W R
V IN _ V T T 1 T P 17
GO OD
E N _P S V
Ze ro O hm Resi stor Settings:
E N1 1 B E R G _3 P I N J P1 R 17 V IN _ V T T 0
1
D6
2
EN _PSV
2
1-2 - V IN_ VTT = V BAT 2 - 3 -- VIN_VTT = 2.5V
3
E N2 3
V 2 _5
C 16 2
1
VBA T
2002 Semtech Corp.
PGO OD 1 PGO OD 2 + 5V _ R U N + 5 V _R U N R E F _I N
R 18
1
10 k
1
3
+ N O_PO P J3 7 8
C 17
2 2N 7 0 02 1 2
Q4
Jum per Se ings: tt
1 - 2 -- EN ABLE + PO WERS AVE
5 6
2 - 3 -- DISA BLE
N O_PO P
O pe n -- Enabl e + FIXED FREQ 4 UENCY
D L1 1 T P 18 1 2 J P2 2 J P3 1 B E R G _2 P I N B E R G _2 P I N G S
2 N O_PO P L X1
Q1A Q1B
D
D1 B _J A C K _ P A I R D H1 2 G 1 PO S N EG
2
S
1 D D1 3 B _J A C K _ P A I R J4
2 N EG
V_T T
1 PO S 1 C 18
Jum per Se ings: tt
1 AG N DF T P 19 1 GN D T P 21
+ N O_PO P
2
2
JP2
JP3
M ODE
O UT O UT IN IN
O UT IN O UT IN
1 2 Vref ON, Vtt OFF (S3 Mode)
Vre and Vtt OFF f
1 T P 20 R 19
Norm al Opera tion Vref a nd Vtt OFF
1
16
AGND
0 0
2
R 20
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SC1486
POWER MANAGEMENT Outline Drawing - TSSOP-28
Land Pattern - TSSOP-28
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2002 Semtech Corp. 17 www.semtech.com

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